In the metallization of high aspect ratio vias and trenches on semiconductor substrates, it is required that the barrier and seed layer have good sidewall coverage.
Ionized Physical Vapor Deposition (IPVD) is used for barrier and seed layer metallization in advanced IC substrates. Ionized PVD provides good sidewall and bottom coverage in via and trench structures. However, as the geometries shrink and as the via dimensions go down below 0.15 micrometers, ionized deposition requirements become more critical. Therefore, it is highly desirable to have an ionized PVD process where bottom and sidewall coverage are well balanced and overhang is minimized.
Accordingly, there is a need to further control step coverage of the metal or the overhang that typically develops during the deposition step.